/**
 * @file    drv_clk.c
 * @brief   CLOCK模块驱动
 * @author  Liu Wei
 * @version 1.0.1
 * @date    2023-04-14
 * 
 * @copyright Copyright (c) 2023 JBD-Energy Storage Technology Co. LTD
 * 
 * @par 修改日志:
 * <table>
 * <tr><th>Date       <th>Version   <th>Author   <th>Description
 * <tr><td>2023-04-14 <td>1.0.1     <td>Liu wei  <td>首次创建
 * </table>
 */

/* includes ------------------------------------------------------------------*/
#include "drv_clk.h"
#include "drv_mcu.h"
/* macro/define --------------------------------------------------------------*/

/* typedef -------------------------------------------------------------------*/

/* local functions -----------------------------------------------------------*/

/* static variables ----------------------------------------------------------*/

/* global variables ----------------------------------------------------------*/

/** ------------------------------------------------------------------------- *
  *                             Global function
 ** ------------------------------------------------------------------------- */
/**
 * @brief  设置系统时钟
 * @param  SYS_CLK_TYPE : 低速、中速、高速
 * @return void
*/
void drv_clk_set_sys(SYS_CLK_TYPE clk_fre)
{
    uint32_t sys_freq = SYS_FREQ_MID;
	if((clk_fre != SYS_FREQ_LOW)
	    	&& (clk_fre != SYS_FREQ_LOW) 
		  	&& (clk_fre != SYS_FREQ_LOW))
	    	sys_freq = SYS_FREQ_MID;
  	else
		    sys_freq = SYS_FREQ_MID;
	  /*---------------------------------------------------------------------------------------------------------*/
    /* Init System Clock                                                                                       */
    /*---------------------------------------------------------------------------------------------------------*/
    /* Unlock protected registers */
    SYS_UnlockReg();
	if ((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0x1) {
        CLK->IOPDCTL = 1;
        //CLK->PMUCTL &= ~(CLK_PMUCTL_DPDHOLDEN_Msk) | CLK_PMUCTL_DPDHOLDEN_Msk;
    }
	SYS->GPF_MFPL = 0x000000EE | SYS_GPF_MFPL_PF2MFP_XT1_OUT | SYS_GPF_MFPL_PF3MFP_XT1_IN;
    /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
    PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);

//    /* Set X32_OUT(PF.4) and X32_IN(PF.5) to input mode */
//    PF->MODE &= ~(GPIO_MODE_MODE4_Msk | GPIO_MODE_MODE5_Msk);

    /* Enable HXT and LXT */
	// CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
    CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; // XTAL12M (HXT) Enabled
   // CLK->PWRCTL |= CLK_PWRCTL_LXTEN_Msk; // 32K (LXT) Enabled

    /* Waiting clock ready */
	// CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
    CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
  //  CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);

	
	CLK->CDUPB = 512;
    CLK->CDLOWB = 510;
	
	CLK->CLKDCTL = CLK_CLKDCTL_HXTFDEN_Msk |
                   CLK_CLKDCTL_HXTFIEN_Msk |
                   CLK_CLKDCTL_LXTFDEN_Msk |
                   CLK_CLKDCTL_LXTFIEN_Msk |
                   CLK_CLKDCTL_HXTFQDEN_Msk|
                   CLK_CLKDCTL_HXTFQIEN_Msk;
	
	// clk_src = CLK->CLKDSTS & CLK_CLKDCTL_HXTFQIEN_Msk;
	
    /* Set core clock as PLL_CLOCK from PLL */
    CLK_SetCoreClock(sys_freq);
    CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2); // PCLK divider set 2

    /* Update System Core Clock */
    /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
    SystemCoreClockUpdate();

    /* Lock protected registers */
    SYS_LockReg();
}

/** ------------------------------------------------------------------------- *
  *                              Local function
 ** ------------------------------------------------------------------------- */

/*********** Copyright (c) 2023 JBD-Energy Storage Technology Co. LTD *********/

